Digital waveform synthesizers are well known and are of widespread use in test equipment and as reference waveform sources In modern communication and other electronic equipment, it has been necessary to develop such synthesizers which are capable of producing waveforms over a wide range of frequencies, typically 0.1 Hz to several MHz, and of high frequency resolution, typically 0.1 Hz. Since it is common in the art to specify a desired frequency as a decimal number, it has become almost a standard in the industry to use a decimally related reference frequency source, typically 10 Hz m(for which high accuracy oscillators are readily available), for direct digital synthesizers. Also because of this convention, it is common to use a binary coded decimal (BCD) adder to accumulate the phase of the synthesized signal to produce the desired frequency from the reference frequency The arrangement disclosed in U.S. Pat. No. 3,735,269 by Jackson is typical of such arrangements.
As used herein, the term "radix" will be used to denote the base of the basic unit of the numerical expression of a number For example, a number in a binary radix is expressed and operated upon solely as a series of digits each expressed as a power of 2 whereas a non-binary radix, such a binary-coded-decimal number, in particular, has a non-binary based digit unit (e.g. 10), values of which being expressed, as is common in the art, with four binary digits, some possible combinations of which are not used.
A block diagram of a common DDS 10 is shown in FIG. 1. This block diagram is typical of either a decimal or binary DDS: The DDS has, as its first stage, a phase accumulator 11, a possible configuration for which is shown in greater detail in FIG. 2, which receives inputs from a reference signal source, f.sub.r, and from another means such as a switch or a register, which specifies the integer phase increment, N. This phase accumulator is typically an accumulating adder or counter or other means for generating a numeric sequence representing phase presettable to an arbitrary number N which generates addresses which are then applied to a wave table 12, such as a waveform memory or look up table, to obtain amplitude values for the waveform at instantaneous phase locations. Alternatively, other arrangements such as mapping or logic devices or any device capable of performing phase to amplitude conversion or mapping can be used The output of the memory is latched at latch 13 .in synchronism with the input reference frequency and applied to a digital-to-analog converter 14. The output of the D/A converter is then filtered to remove spurious frequency components higher than the Nyquist frequency and, thus, produce the desired waveform at the desired frequency. This arrangement is well understood in the art and further detailed disclosure is not deemed necessary. If it is desired that the DDS perform in a decimally related fashion, the phase accumulator will necessarily be organized in a decimal radix fashion, for instance, using logic circuitry which accumulates or counts and provides addresses in BCD or similar decimal code.
Using a decimal radix for waveform synthesis, while maximizing operator convenience, has numerous drawbacks from the standpoints of hardware, efficiency and accuracy These drawbacks stem largely from the fact that BCD is only approximately 60% as efficient in terms of storage, latches, etc as pure binary; requiring four bits to access ten addresses rather than sixteen as in binary. Further, phase accumulation at high phase resolutions requires carry operations which, while well understood and not particularly complex, do require more logic operations which require some finite time interval. This represents a significant limitation in high frequency synthesis As a design minimum, accommodation of such operations requires a complex clock arrangement and tends to introduce timing inaccuracies in the phase accumulator or elsewhere in the system, such as at the waveform memory or the digital to analog converter. Such timing errors tend, in turn, to introduce errors into the output waveform in the form of distortion and spurious signals, resulting in degradation of waveform fidelity. The above method is also inefficient in utilization of waveform memory as compared to an all binary system. Memory access is also impaired since the waveform memory addresses may not be sequentially scanned because of the codes which would be missing from nondecimal locations.
Other known types of digital waveform generators have avoided these problems by employing binary design throughout at significant cost to operator convenience and at some cost in the difficulty of design. Specifically, if it is desired to accurately generate a decimally specified frequency, the reference frequency must be a integral power of 2, which is difficult to specify decimally during initial reference oscillator design and difficult to maintain without complex monitoring arrangements Also, since the electronic equipment with which the digital waveform synthesizer is used is likely to have a decimally related clock, coherence is similarly difficult to establish and maintain Finally, the accuracy and resolution of the frequency of the synthesized waveform are difficult to specify in decimal notation and the effect of errors in such frequency or frequency resolution are difficult to predict; further exacerbating the difficulty to an operator in the use of non-decimal systems.
Numerous approaches have been used to obtain coherence of an oscillator with a reference source. Among these, phase lOcked loops are regarded as most desirable since they are well-understood and require only a relatively small number of simple components and, hence, are well suited to integration and inclusion with other circuits on an integrated circuit chip.
Another difficulty has been encountered with systems using phase locked loops to maintain frequency coherence in waveform synthesis systems in that when it was desired to change the frequency of the synthesized waveform, it was common to do so by changing the division factor in the phase-locked loop. This results in loss of phase coherence for some finite acquisition time while a lock condition of the phase-locked loop is reestablished Because of this finite acquisition time, signal generators which maintained phase coherence with phase-locked loops were unsuitable for producing signals necessary for some applications such as frequency shift keying, where rapid frequency switching is required, without resorting to complex arrangements such as plural phase-locked loops or waveform memory manipulations.
In summary, therefore, the prior art has failed to provide a direct digital synthesizer (DDS) capable of high accuracy, resolution and fidelity which is also capable of producing decimally related and specified frequencies with a decimally specified resolution and coherence to a decimal based frequency reference source with no acquisition time when synthesized frequency is changed and ease of operator use.